Hardware Implementation of Improved Adaptive NoC Router with Flit Flow History based Load Balancing Selection Strategy

To improve load balancing in NoCs several techniques exists in literature like Regional Congestion Awareness (RCA) and similar techniques. Also there are some techniques based on output port selection like count of free virtual channels, count of fluid buffers, buffer occupancy time at reachable downstream neighbors and flit flow history based algorithm named as Tracker. Among these techniques, Tracker has performed significantly better than others. However, Tracker has been simulated and verified using NoC simulation tool and no hardware implementation of flit flow based algorithm exists in literature yet. The proposed work is anew in the regard that no hardware implementation of Tracker architecture have been seen till now in the research literature of Network on chip. It implements improved flit flow based technique used by Tracker implemented on programmable hardware (Xilinx Virtex-5 FPGA) and achieves significant frequency of 686.81 MHz as validated by experimental synthesized results. The innovation in the existing architecture was brought about by insertion of additional buffers in the tracker internal logic to achieve better area / performance trade off for chip multiprocessors. Keywords— NoC, Tracker, Adaptive routing, MOE, Load balancing routing, Virtual Channel router, Verilog, Virtex FPGA.